`timescale 1ns/1ps

module  rptr_overmark(
                 //output
                  overmark,
                 //input
                  rd_clk,
                  rd_rst,
                  rd_clr,
                  rp_bin,                  
                  wp_s,
                  pm         
                 );
                 
  parameter aw=10;  

output         overmark;             //high active

input          rd_clk;
input          rd_rst;
input          rd_clr;
input  [aw:0]  rp_bin;
input  [aw:0]  wp_s;
input  [2:0]   pm;

/////////////////////////////////////////////////////////////////////
//
//	local wires
//
reg             overmark;

wire	[aw:0]		wp_bin_x;

reg 	[aw:0]		pr_diff;    

	   
////////////////////////////////////////////////////////////////////
//
//	belowmark state 
//
assign wp_bin_x = wp_s ^ {1'b0, wp_bin_x[aw:1]};	// convert gray to binary

always @(posedge rd_clk or negedge rd_rst)	
	if(!rd_rst)	pr_diff <=#1 {aw+1{1'b0}};
	else
	if(rd_clr)	pr_diff <=#1 {aw+1{1'b0}}; 
	else
	 pr_diff <=#1 wp_bin_x + ~rp_bin +1;


always @(posedge rd_clk or negedge rd_rst)	
	if(!rd_rst)	overmark <=#1 1;
	else
	if(rd_clr)	overmark <=#1 1; 
	else
  if( pr_diff[aw:aw-3] >= pm)
    overmark<=#1  0;
  else
    overmark<=#1  1; 	       
        
endmodule    